`timescale 1ns / 1ps
`include "ExceptStruct.vh"
module EXEMEM (
  input         clk,
  input         rst,
  input         stall,
  input         flush,
  input  [63:0] EXE_pc,
  input  [31:0] EXE_inst,
  input         EXE_valid,
  input  [63:0] EXE_data1,
  input  [63:0] EXE_data2,
  input  [4:0]  EXE_rs1,
  input  [4:0]  EXE_rs2,
  input  [4:0]  EXE_rd,
  input         EXE_rs1_use,
  input         EXE_rs2_use,
  input         EXE_we_reg,
  input         EXE_we_mem,
  input  [1:0]  EXE_wb_sel,
  input  [2:0]  EXE_data_width,
  input  [63:0] EXE_pc_4,
  input         EXE_npc_sel,
  input  [63:0] EXE_alu_res,
  input         EXE_re_mem,
  input  ExceptStruct::ExceptPack       EXE_except,
  input         EXE_csr_we,
  input  [63:0] EXE_csr_res,
  input  [63:0] EXE_csr_val,
 
  output  reg [63:0] MEM_pc,
  output  reg [31:0] MEM_inst,
  output  reg        MEM_valid,
  output  reg [63:0] MEM_data1,
  output  reg [63:0] MEM_data2,
  output  reg [4:0]  MEM_rs1,
  output  reg [4:0]  MEM_rs2,
  output  reg [4:0]  MEM_rd,
  output  reg        MEM_rs1_use,
  output  reg        MEM_rs2_use,
  output  reg        MEM_we_reg,
  output  reg        MEM_we_mem,
  output  reg [1:0]  MEM_wb_sel,
  output  reg [2:0]  MEM_data_width,
  output  reg [63:0] MEM_pc_4,
  output  reg        MEM_npc_sel,
  output  reg [63:0] MEM_alu_res,
  output  reg        MEM_re_mem,
  output  ExceptStruct::ExceptPack    MEM_except,
  output  reg        MEM_csr_we,
  output  reg [63:0] MEM_csr_res,
  output  reg [63:0] MEM_csr_val
);
import ExceptStruct::ExceptPack;
always @(posedge clk) begin
  if (rst | flush) begin
    MEM_pc <= 64'b0;
    MEM_inst <= 32'b0;
    MEM_valid <= 1'b0;
    MEM_data1 <= 64'b0;
    MEM_data2 <= 64'b0;
    MEM_rs1 <= 5'b0;
    MEM_rs2 <= 5'b0;
    MEM_rd <= 5'b0;
    MEM_rs1_use <= 1'b0;
    MEM_rs2_use <= 1'b0;
    MEM_we_reg <= 1'b0;
    MEM_we_mem <= 1'b0;
    MEM_wb_sel <= 2'b0;
    MEM_data_width <= 3'b0;
    MEM_pc_4 <= 64'b0;
    MEM_npc_sel <= 1'b0;
    MEM_alu_res <= 64'b0;
    MEM_re_mem <= 1'b0;
    MEM_csr_we <= 1'b0;
    MEM_csr_res <= 64'b0;
    MEM_csr_val <= 64'b0;
    MEM_except.ecause <= 0;
    MEM_except.epc <= 0;
    MEM_except.etval <= 0;
    MEM_except.except <= 0;
  end
  else if (~stall) begin
    MEM_pc <= EXE_pc;
    MEM_inst <= EXE_inst;
    MEM_valid <= EXE_valid;
    MEM_data1 <= EXE_data1;
    MEM_data2 <= EXE_data2;
    MEM_rs1 <= EXE_rs1;
    MEM_rs2 <= EXE_rs2;
    MEM_rd <= EXE_rd;
    MEM_rs1_use <= EXE_rs1_use;
    MEM_rs2_use <= EXE_rs2_use;
    MEM_we_reg <= EXE_we_reg;
    MEM_we_mem <= EXE_we_mem;
    MEM_wb_sel <= EXE_wb_sel;
    MEM_data_width <= EXE_data_width;
    MEM_pc_4 <= EXE_pc_4;
    MEM_npc_sel <= EXE_npc_sel;
    MEM_alu_res <= EXE_alu_res;
    MEM_re_mem <= EXE_re_mem;
    MEM_except <= EXE_except;
    MEM_csr_we <= EXE_csr_we;
    MEM_csr_res <= EXE_csr_res;
    MEM_csr_val <= EXE_csr_val;
  end
end

endmodule